It _is_ RISC-V Vector extensions, so a very specific ISA in mind at the very least. There's another extension (not ratified I think) called Packed SIMD for RISC-V, but this isn't about that.
The name, yes, but going by name is a bad idea as the V in AVX also stands for Vector.
BTW, you'll be disappointed if you think of the P extension as something like SSE/AVX. The target for it is way lower power/perf, like a stripped-down MMX.
My point was about the underlying hardware implementation, specifically:
> "As shown in Figure 1-3, array processors scale performance spatially by replicating processing elements, while vector processors scale performance temporally by streaming data through pipelined functional units"
Applies to the hadware implementation, not the ISA, which is not made clear by the text.
You can implement AVX-512 with smaler data path then register width and "scale performance temporally by streaming data through pipelined functional units". Zen4 is a simple example of this, but there is nothing stopping you from implementing AVX-512 on top of heavily temporaly pipelined 64-bit wide execution units.
Similarly, you can implement RVV with a smaller data path than VLEN, but you can also implement it as a bog-standard SIMD processor.
The only thing that slightly complicates the comparison is LMUL, but it is fundamentally equivilant to unrolling.
The substantial difference between Vector and SIMD ISAs is imo only the existence of a vl-based predication mechanism.
If a SIMD ISA has a fixed register width or not, allowing you to write vector-length agnostic code, is an independent dimension of the ISA design. E
.g. the Cray-1 was without a doubt a Vector processor, but the vector registers on all compatible platforms had the exact same length. It did, however, have the mentioned vl-based predication mechanism.
You could take AVX10/128, AVX10/256 and AVX10/512, overlap their instruction encodings, and end up with a scalable SIMD ISA, for which you can write vector length agnostic code, but that doesn't make it a Vector ISA any more than it was before.
> The name, yes, but going by name is a bad idea as the V in AVX also stands for Vector.
Now I get your point after reading more of the linked page. Yes. It is very implementation specific.
One of the things about RVV (and in general any vector ISA) is that the data path can be different enough between different implementations such that specific rules of thumb for hand tuning most probably won’t carry over. As you say it is true of even sufficiently advanced SIMD architectures like AVX.
That was a bit overblown, due to my lack of knowlage about MMX. It has a lot more things than MMX.
But the core idea behind the P extension was to reuse the GPRs to do SIMD operations with little additional implementation cost.
As sibling said, stripped down in the sense it doesn’t have dedicated registers. In terms of supported functions it’s somewhere close to MMX.
I don’t personally like it because it still ends up with all the headache of building most of a vector subsystem (data path, functional units,…) while _only_ pretty much reducing one special vector file.
I'm coming around to the idea that we _should_ really be using "l" or maybe "r" instead of "zh" for the ழ. At least it's closer in pronunciation and there's a chance someone can work their way to it. Zh is like "we don't have an exact match so we'll repurpose a letter we don't use". It has no phonetic relevance.
Tamil is my mother tongue and I agree 100%. And like insisting that sentences shouldn't end with a preposition, or "you should say GNU/Linux, not Linux", it's no way to make friends and influence people.
I think the decline of manual transmission is different from self-driving. Manuals, you could argue are a technological progression that doesn’t change the fundamental economics or sociology of driving. But self-driving has issues far beyond the technology. Like liability, like ownership of vehicles, availability, traffic rules,…
I’m not even sure if, outside of highly mapped environments it even makes sense.
Or it collapses when the seniors have to retire anyway. Who instructs the LLM when there’s nobody who understands the business?
I’m sure the plan is to create a paperclip maximizing company which is fully AI. And the sea turned salty because nobody remembered how to turn it off.
In the Before Times we used to do programming interviews with “you can use Google and stack overflow” for precisely this reason. We weren’t testing for encyclopaedic knowledge - we were testing to see if the candidate could solve a problem.
But the hard part is designing the problem so that it exercises skill.
Over the years it’s kind of becoming clear that “running major businesses” is kind of orthogonal to “having emotional integrity”. In larger businesses it’s mediated by layers. But just take a look at some of the deranged tweetstorms we’ve become used to in recent times.
Good to see that we're being noticed. But we all still need to deploy (in scale) to make anything worthwhile.