VHDL / Verilog is very different, but not necessarily harder per-se. It's just people spend 4 years learning "normal" programming, and at best have a one-semester course which uses VHDL.
The issue I see is they are slow to compile. I write them daily and it's not that hard to lean when you grok the parallel nature, but generating the HW usually takes at least 10 to 30 mins for a medium sized block, that is a bit of a barrier to entry.
As an FPGA dev, I tend to think of HDLs akin to HTML than “code”. It’s just a DSL to describe a graph. Actually pretty similar to how tensorflow is designed.
But yes, a software stack would help.